The theoretical performance advantages of gallium arsenide (GaAs)/gallium aluminium arsenide (GaAlAs) III-V bipolar transistors over their silicon counterparts are well known. At present, however, higher bipolar circuit speeds have been obtained for silicon devices. There is one reason for this discrepancy: highly advanced silicon technology makes possible the fabrication of devices of extremely small size hitherto unattainable with current GaAs processes. In particular, the "Super Self-Aligned" process (Sakai T., et al., "Prospects of SSI technology for high speed LSI", IEDM 1985, Tech. Dig., p18.) represents the state of the art for silicon.
There are considerable obstacles to the realisation of such a process in GaAs; silicon has intrinsic advantages such as a native oxide, the possibility of polycrystalline silicon overgrowth for extended contacts and impurity diffusion, and a common contact metallurgy for p-type and n-type regions. Published schemes for self-alignment of GaAs/GaAlAs bipolar devices (e.g. Asbeck P.M., "Heterojunction Bipolar Transistors", IEDM 1985, Short course: Digital III-V Device and Circuit Technology", course notes p114., and, Izawa T., et al., "AlGaAs/GaAs Heterojunction Bipolar Transistors", IEDM 1985, Tech. Dig., p328.) have suffered from difficulties involved in contacting the base layer due to the need to remove any parasitic GaAs/GaAs homojunction regions between emitter and base. Achieving a low contact resistance to the emitter is also problematic. Scaling to the dimensions typified by the self-aligned silicon device (above) presents great problems in these schemes.